Design and Verification of Faster Multiplier

The multiplier and multiplier-and-accumulator (MAC) are the essential elements of the digital signal processing. Multiplication involves two basic operations: the generation of partial products and their accumulation. Partial products can be reduced by using the Radix_4 modified Booth algorithm. The design of a binary signed-digit partial product generator, which expresses each normal binary operand in one’s complement form with an extra bit denoting the sign bit of the operand. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was improved. The CSA tree has the modified array for the sign extension in order to increase the bit density of the operands. The parallel multipliers like radix 4 modified booth multiplier do the computations using lesser adders and lesser iterative steps. This is very important criteria because in the fabrication of chips and high performance system requires components which are as small as possible. The Multiplier and Accumulator can be adapted to various fields requiring high performance such as signal processing areas. Modelsim is used for logical verification, and further synthesizing it on Xilinx-ISE tool using target technology